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ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 20 features ? 72-pin jedec standard single-in-line memory module ? performance: ? high performance cmos process ? single 5v, 0.5v power supply ? all inputs & outputs are fully ttl & cmos compatible ? extended data out (edo) access cycle ? refresh modes: ras-only, cbr and hidden refresh ? 2048 refresh cycles distributed across 32ms ? 11/11 addressing (row/column) ? optimized for use in byte-write non-parity appli- cations ? sn/pb tab versions only ? 16mb versions in tsop or soj packages. ? 32mb version only in soj package. description the IBM11D8325B is a 32mb industry standard 72-pin 4-byte single in-line memory module (simm) manufactured using edo drams. the use of edo drams allows for a reduction in page mode cycle time from 40ns (fast page) to 25ns (edo, 60ns sort). the module is organized as an 8mx32 high speed memory array, and is configured as two 4mx32 banks -each independently selectable via unique ras inputs. the assembly is manufactured with sixteen 4mx4 devices, each in a 300mil soj package, and is compatible with the jedec 72-pin simm standard. the ibm11d4325b is a 16mb half populated ver- sion, manufactured with eight 4mx4 devices each in a 300mil tsop or soj package. the ibm 72-pin simms provide a high performance, flexible 4-byte interface in a 4.25 long footprint. -60 -70 t rac ras access time 60ns 70ns t cac cas access time 15ns 20ns t aa access time from address 30ns 35ns t rc cycle time 104ns 124ns t hpc edo mode cycle time 25ns 30ns card outline 1 36 37 72 ibm11d8320b8m x 3211/11, 5.0v, sn/pb. ibm11e8320b8m x 3211/11, 5.0v, au. discontinuted (9/98 - last order; 3/99 last ship)
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 20 50h7996 sa14-4341-02 revised 8/96 ibm11d4325b IBM11D8325B 4m/8m x 32 dram module pin description ras0, ras2 row address strobe (16mb) ras0 - ras3 row address strobe (32mb) cas0 - cas3 column address strobe we read/write input a0 - a10 address inputs dq0-7, 9-16, 18-25, 27-34 data input/output v cc power (+5v) v ss ground nc no connect pd1 - pd4 presence detects pinout pin # name pin # name pin # name 1 v ss 25 dq24 49 dq9 2 dq0 26 dq7 50 dq27 3 dq18 27 dq25 51 dq10 4 dq1 28 a7 52 dq28 5 dq19 29 nc 53 dq11 6 dq2 30 v cc 54 dq29 7 dq20 31 a8 55 dq12 8 dq3 32 a9 56 dq30 9 dq21 33 ras3* 57 dq13 10 v cc 34 ras2 58 dq31 11 nc 35 nc 59 v cc 12 a0 36 nc 60 dq32 13 a1 37 nc 61 dq14 14 a2 38 nc 62 dq33 15 a3 39 v ss 63 dq15 16 a4 40 cas0 64 dq34 17 a5 41 cas2 65 dq16 18 a6 42 cas3 66 nc 19 a10 43 cas1 67 pd1 20 dq4 44 ras0 68 pd2 21 dq22 45 ras1* 69 pd3 22 dq5 46 nc 70 pd4 23 dq23 47 we 71 nc 24 dq6 48 nc 72 v ss ordering information part number organization speed addr. leads dimensions package notes ibm11d4325b-60 4m x 32 60ns 11/11 sn/pb 4.25 x 1 x .205 soj ibm11d4325b-70 70ns ibm11d4325b-60j 60ns 1 ibm11d4325b-70j 70ns 1 ibm11d4325b-60 60ns 4.25 x 1 x .104 tsop ibm11d4325b-70 70ns ibm11d4325b-60t 60ns 1 ibm11d4325b-70t 70ns 1 IBM11D8325B-60 8m x 32 60ns 4.25 x 1 x .360 soj IBM11D8325B-70 70ns IBM11D8325B-60j 60ns 1 IBM11D8325B-70j 70ns 1 1. dram package designator appended to speed portion of part number on assemblies beginning with dram die rev e. discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 20 block diagram 11 11 dq9 11 11 a0-a10 we cas0 ras0 cas1 11 11 dq0 cas2 ras2 11 11 cas3 dq18 we cas ras oe dq1-4 a0-a10 u1 we cas ras oe dq1-4 a0-a10 u2 we cas ras oe dq1-4 a0-a10 u3 we cas ras oe dq1-4 a0-a10 u5 we cas ras oe dq1-4 a0-a10 u6 we cas ras oe dq1-4 a0-a10 u7 we cas ras oe dq1-4 a0-a10 u8 we cas ras oe dq1-4 a0-a10 u4 dq27 dq7 dq25 dq34 dq16 11 11 dq9 11 11 a0-a10 we cas0 ras1 cas1 11 11 dq0 cas2 ras3 11 11 cas3 dq18 we cas ras oe dq1-4 a0-a10 u15 we cas ras oe dq1-4 a0-a10 u16 we cas ras oe dq1-4 a0-a10 u11 we cas ras oe dq1-4 a0-a10 u13 we cas ras oe dq1-4 a0-a10 u14 we cas ras oe dq1-4 a0-a10 u9 we cas ras oe dq1-4 a0-a10 u10 we cas ras oe dq1-4 a0-a10 u12 dq27 dq7 dq25 dq34 dq16 applies to both 16mb and 32mb simms applies to 32mb simm only discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 20 50h7996 sa14-4341-02 revised 8/96 truth table function ras cas we row address column address all dq bits standby h h ? x x x x high impedance read l l h row col valid data out early-write l l l row col valid data in edo mode - read: 1st cycle l h ? l h row col valid data out subsequent cycles l h ? l h n/a col valid data out edo mode - write: 1st cycle l h ? l l row col valid data in subsequent cycles l h ? l l n/a col valid data in ras-only refresh l h x row n/a high impedance cas-before- ras refresh h ? l l h x x high impedance hidden refresh read l ? h ? l l h row col data out write l ? h ? l l l row col data in presence detect pin 4m x 32 8m x 32 -60 -70 -60 -70 pd1 v ss v ss nc nc pd2 nc nc v ss v ss pd3 nc v ss nc v ss pd4 nc nc nc nc 1. nc= open , v ss = gnd discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 20 absolute maximum ratings symbol parameter rating units notes v cc power supply voltage -1.0 to +7.0 v 1 v in input voltage -0.5 to min (v cc + 0.5, 7.0) v 1 v out output voltage -0.5 to min (v cc + 0.5, 7.0) v1 t opr operating temperature 0 to +70 c 1 t stg storage temperature -55 to +125 c 1 p d power dissipation 3.74 (16mb) 7.5 (32mb) w 1, 2 i out short circuit output current 50 ma 1 1. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functional operation at or above the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended peri- ods may affect reliability. 2. maximum power occurs when all banks are active (refresh cycle). recommended dc operating conditions (t a = 0 to 70 c) symbol parameter min typ max units notes v cc supply voltage 4.5 5.0 5.5 v 1 v ih input high voltage 2.4 v cc + 0.5 v 1, 2 v il input low voltage -0.5 0.8 v 1, 2 1. all voltages referenced to v ss . 2. v ih may overshoot to v cc + 2.0v for pulse widths of 4.0ns (or v cc + 1.0v for 8.0ns). additionally, v il may undershoot to -2.0v for pulse widths 4.0ns (or -1.0v for 8.0ns). pulse widths measured at 50% points with amplitude measured peak to dc refer- ence. capacitance (t a = 0 to +70 c, v cc = 5.0v 0.5v) symbol parameter 4m x 32 max 8m x 32 max units c i1 input capacitance (a0-a10) 55 98 pf c i2 input capacitance (16mb: ras0, 32mb: ras0, 1) 40 40 pf c i3 input capacitance (16mb: ras2, 32mb: ras2, 3) 40 40 pf c i4 input capacitance ( cas) 25 40 pf c i5 input capacitance ( we) 66 127 pf c i/o output capacitance (dq0 - dq34) 13 25 pf discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 20 50h7996 sa14-4341-02 revised 8/96 dc electrical characteristics (t a = 0 to +70 c, v cc = 5.0v 0.5v) symbol parameter 4m x 32 8m x 32 units notes min max min max i cc1 operating current average power supply operating current ( ras, cas, address cycling: t rc = t rc min) -60 680 696 ma 1, 2, 3 -70 600 616 i cc2 standby current (ttl) power supply standby current ( ras = cas 3 v ih ) 16 32 ma i cc3 ras only refresh current average power supply current, ras only mode ( ras cycling, cas 3 v ih : t rc = t rc min) -60 680 696 ma 1, 3, 4 -70 600 616 i cc4 edo mode current average power supply current, edo mode ( ras = v il , cas, address cycling: t hpc = t hpc min) -60 520 536 ma 1, 2, 3 -70 440 450 i cc5 standby current (cmos) power supply standby current ( ras = cas = v cc - 0.2v) 816ma i cc6 cas before ras refresh current average power supply current, cas before ras mode ( ras, cas, cycling: t rc = t rc min) -60 680 696 ma 1, 3, 4 -70 600 616 i i(l) input leakage current input leakage current, any input (0.0 v in (v cc < 6.0v)) all other pins not under test = 0v ras -40 +40 -40 +40 m a cas -20 +20 -40 +40 all others -80 +80 -160 +160 i o(l) output leakage current (d out is disabled, 0.0 v out v cc ) -10 +10 -20 +20 m a v oh output high level output "h" level voltage (i out = -5ma) 2.4 2.4 v v ol output low level output "l" level voltage (i out = +4.2ma) 0.4 0.4 v 1. i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 2. i cc1 , i cc4 depend on output loading. speci?ed values are obtained with the output open. 3. address can be changed once or less while ras = v il . in the case of i cc4 , it can be changed once or less when cas = v ih 4. refresh current is speci?ed for 1 bank active and 1 bank standby. discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 20 ac characteristics (t a = 0 to +70 c, v cc = 5 0.5v) 1. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 2. an initial pause of 200 m s is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles is required. 3. ac measurements assume t t = 2ns. 4. valid column addresses are a0 through a10. read, write, and refresh cycles (common parameters) symbol parameter -60 -70 units notes min max min max t rc random read or write cycle time 104 124 ns t rp ras precharge time 40 50 ns t cp cas precharge time 10 10 ns t ras ras pulse width 60 10k 70 16k ns t cas cas pulse width 10 10k 12 10k ns t asr row address setup time 0 0 ns t rah row address hold time 10 10 ns t asc column address setup time 0 0 ns t cah column address hold time 10 10 ns t rcd ras to cas delay time 14 45 14 50 ns 1 t rad ras to column address delay time 12 30 12 35 ns 2 t rsh ras hold time 10 12 ns t csh cas hold time 50 55 ns t crp cas to ras precharge time 5 5 ns t dzc cas delay time from d in 00ns t ar column address hold time referenced to ras ns 3 t t transition time (rise and fall) 2 30 2 30 ns 1. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only: if t rcd is greater than the specified t rcd (max) limit, then access time is controlled by t cac . 2. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max) limit, then access time is controlled by t aa . 3. this parameter is not applicable to this product, but applies to a related product in this family. discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 20 50h7996 sa14-4341-02 revised 8/96 write cycle symbol parameter -60 -70 units min max min max t wcs write command set up time 00ns t wch write command hold time 10 12 ns t wp write command pulse width 10 12 ns t ds d in setup time 00ns t dh d in hold time 10 12 ns read cycle symbol parameter -60 -70 units notes min max min max t rac access time from ras 6070ns 1, 2 t cac access time from cas 1520ns 1, 2 t aa access time from address 30 35 ns 1, 2 t rcs read command setup time 0 0 ns t rch read command hold time to cas 0 0 ns 3 t rrh read command hold time to ras 0 0 ns 3 t ral column address to ras lead time 30 35 ns t clz cas to output in low-z 0 0 ns t cdd cas to d in delay time 1515ns t off output buffer turn-off delay 15 15 ns 4 1. measured with the specified current load and 100pf. 2. access time is determined by the latter of t rac , t cac , t cpa , t aa . 3. either t rch or t rrh must be satis?ed for a read cycle. 4. t off (max) de?nes the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 20 hyper page mode (extended data out) cycle symbol parameter -60 -70 units notes min. max. min. max. t hcas cas pulse width (edo mode) 10 10k 12 10k ns t hpc edo mode cycle time (read/write) 25 30 ns t doh data-out hold time from cas 5 5 ns t whz output buffer turn-off delay from we 0 10 0 15 ns t wpz we pulse width to output disable at cas high 10 10 ns t cprh ras hold time from cas precharge 35 40 ns t cpa access time from cas precharge 35 40 ns 1, 2 t rasp edo mode ras pulse width 60 125k 70 125k ns 1. access time assumes a load of 100pf at v ol = 0.8v and v oh = 2v. 2. access time is determined by the latter of t rac, t cac, t cpa, t aa. refresh cycle symbol parameter -60 -70 units notes min max min max t chr cas hold time ( cas before ras refresh cycle) 1010ns t csr cas setup time ( cas before ras refresh cycle) 55ns t wrp we setup time ( cas before ras refresh cycle) 1010ns t wrh we hold time ( cas before ras refresh cycle) 1010ns t rpc ras precharge to cas hold time 5 5 ns t ref refresh period 32 32 ms 1 1. 2048 refreshes are required every 32ms. discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 20 50h7996 sa14-4341-02 revised 8/96 read cycle ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rcs t dzc t clz t cac t rac hi-z hi-z t rrh : h or l t rcd hi-z t rsh t ral t aa t cdd t rch t off t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. cas t ar discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 20 write cycle (early write) t rc ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rcd t csh t crp t rah t asc t cah t asr t rad t wcs hi-z : h or l valid data in t wch t ds t dh t cas t rsh t wp cas t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional . doing so will facilitate compatibility with future edo drams. discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 20 50h7996 sa14-4341-02 revised 8/96 extended data out mode read cycle t rp data out 1 data out 2 we ras row address column 1 column 2 column n t doh t doh t clz t cac v ih v il t asr t rah t asc t asc t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t wp t cac data out n t off t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t cah cas t ar t hcas discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 20 extended data out mode read cycle ( we control) t rp data out 1 data out 2 we ras row address column 1 column 2 column n t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t hcas t wpz t wpz t rch t rcs t rcs t rch t whz t whz cas t ar discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 20 50h7996 sa14-4341-02 revised 8/96 extended data out mode early write cycle t rp ras row address we column 1 column 2 column n data in 1 data in 2 data in n t asr t rah t cah t wch t dh d in t rasp t rsh t hcas t hcas t hpc t rad t asc t asc t csh t cah t asc t cah t wch t wcs t wch t wcs t wcs t ds t ds t dh t dh t ds : h or l t cwl t rwl t wp t wp t wp v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t dhr cas t ar t hcas t ral discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 20 ras only refresh cycle ras v ih v il v ih v il address v ih v il d out v oh v ol row t ras t rp t rc t rah t asr hi-z note: we, d in are h or l t rpc t crp : h or l cas discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 20 50h7996 sa14-4341-02 revised 8/96 cas before ras refresh cycle ras v ih v il v ih v il we v ih v il d in v oh v ol t ras t rp d out v oh v ol hi-z : h or l t off hi-z t chr rc t t wrh t wrp t note: address is h or l rpc t cp t cdd t rpc t csr t wrh t wrp t csr cas discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 20 hidden refresh cycle (read) ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in row column t ras t ras t rp t rc t crp t rah t asc t cah t asr t rad t rcs t dzc t cdd t clz t cac t rac hi-z hi-z : h or l t rp t chr rsh t rcd t t rrh t wrp t wrh t rc t aa t ral cas valid data out t off hi-z discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 20 50h7996 sa14-4341-02 revised 8/96 hidden refresh cycle (write) ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in row column valid data t ras t ras t rp t rc t crp t rah t asc t cah t asr hi-z : h or l t rp t chr rsh t t ds t dh t wch wcs t t wrp t wrh t rc t wp t rcd cas discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module 50h7996 sa14-4341-02 revised 8/96 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 20 layout drawing 107.95 4.25 25.4 95.25 3.75 ref. 44.45 1.75 1.27 pitch .050 1.00 width .039 6.35 .250 10.16 (2x) 0 3.1877 .1255 front 2.03 .08 6.35 1.00 .400 .25 note: all dimensions are typical unless otherwise stated. 101.190 3.983 millimeters inches 2.65 .104 max. 5.848 side (16mb tsop) 1.27 + _ .050 + _ .1016 .0762 .004 .003 .230 min. 9.14 .360 max. 7.239 side (32mb) 1.27 + _ .050 + _ .1016 .0762 .004 .003 .285 min. 5.848 .285 min. 5.2 .205 max. 5.848 side (16mb soj) 1.27 + _ .050 + _ .1016 .0762 .004 .003 .230 min. discontinuted (9/98 - last order; 3/99 last ship)
ibm11d4325b IBM11D8325B 4m/8m x 32 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 20 50h7996 sa14-4341-02 revised 8/96 revision log rev contents of modi?cation 3/96 initial release of combined spec for 4m x 32, 8m x 32 removed gold-tab versions cbr timing diagram changed to allow cas to remain low for back-to-back cbr cycles (originally released as spec #s 26h3207 and 26h3208) 5/96 added 16mb tsop version 8/96 corrected typos discontinuted (9/98 - last order; 3/99 last ship)
intern ational business machines corp.1996 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com a discontinuted (9/98 - last order; 3/99 last ship)

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